DRAM缩放需要新材料工程解决方案

Demand for lower-cost, higher-density DRAM has never been greater as the Internet of Things (IoT), autonomous vehicles and 5G connectivity add more devices and exponentially increase data, further straining the edge and cloud computing infrastructure. IoT devices are estimated to total 500 billion by 2030 and generate a yottabyte of data per year—that’s ten to the power of 24 bytes.

数据的价值来自处理它，越来越多地通过使用AI来获得可行的见解。这需要负担得起的高性能DRAM，并且需要很多。DRAM制造商正在竞争，以克服许多身体限制，如果尚未解决，将阻碍DRAM性能，功率，区域和成本。该博客将研究进一步扩展电容器和外围电路的挑战和机遇。

每个DRAM存储器单元都由晶体管和电容器组成，这些电容器需要一起扩展以使位密度增加。电容器使用金属构造器金属架构存储电荷。一个深孔衬有薄金属底部电极，通常由硝化钛制成。然后，沉积了一层薄薄的高k绝缘介电材料。最后，沉积了第二个金属电极（见图1）。

Capacitor Aspect Ratio Scaling

The storage capacitor’s charge is proportional to the surface area of the inside and outside surfaces of the deep hole. The ratio of the hole’s height to its diameter is the aspect ratio. 2D scaling of the memory cells causes the diameter to shrink and, to maintain adequate surface area and charge, the aspect ratio must increase. To continue 2D scaling, chipmakers keep squeezing the capacitor diameter, which pushes the aspect ratio to the extreme.

虽然是一个实用的想法，但这种方法正在达到常规图案技术的物理极限。具体而言，电容器的孔是用由无定形多硅胶制成的牺牲硬口罩来定义的，这些掩模被蚀刻到蚀刻，从而形成了一个模板，以使后续蚀刻变成厚的模具，从而产生越来越狭窄的电容器孔。

As high-energy ions etch the capacitor holes, they also eat away at the hard mask. The higher the aspect ratio, the greater the risk that the hard mask is eroded before the capacitor hole is fully formed, which ruins the chip.

缓解这种风险的一种方法是增加硬面膜的厚度，但这也会引起问题。较高的硬面膜的长宽比加上较窄的电容器孔的组合使得完成蚀刻并去除所有蚀刻副产品变得越来越困难。这些副产品会导致扭曲，弯曲，蚀刻和其他物理缺陷（见图2）。

What DRAM makers really need in order to continue scaling is a denser, harder mask material that erodes at a substantially slower rate than the underlying capacitor mold. This thinner hard mask would allow deeper etches along with byproduct removal for perfectly cylindrical and straight capacitor holes with evenly matched depths.

Periphery Circuitry Scaling

A second opportunity to continue DRAM shrinking is to reduce the size of the peripheral circuitry area which consists of the logic transistors and interconnect wiring that surrounds the DRAM cell array (see Figure 3). If the memory cells scale but the periphery circuitry doesn’t, then the periphery takes up an increasing percentage of the die size. The logic is important: it helps determine the performance and power consumption of today’s high-speed DDR4 and emerging DDR5 DRAMs. Each of the metal lines that connect the logic transistors to the cell areas needs to be surrounded by an insulating dielectric material to prevent interference between electrical signals, and the thickness of this dielectric is another key factor impacting scaling. For the past 25 years, DRAM makers have used one of two silicon oxides—silane and tetraethoxysilane (TEOS)—as the dielectric material.

Today, DRAM makers are facing the same dielectric scaling challenges faced by leading-edge logic makers around 20 years ago. Beyond a certain point, thinning the dielectrics brings the metal lines so close together that capacitive coupling increases. As a result, the device suffers from increased power consumption, reduced performance, excess heat and potential reliability issues. In logic scaling, the solution was new copper low-k interconnects. In DRAM, the time for a new material that allows metal lines to be placed closer together without causing signal interference is now.

New Materials Research

These DRAM scaling materials engineering challenges—involving patterning hard masks and insulating dielectrics—have been the subject of intense research. In my next blog, I’ll discuss new materials that Applied Materials has been developing to help DRAM makers extend their product roadmaps to meet the world’s growing need for affordable, high-performance DRAMs.