是时候制作一本新的剧本来查找和纠正高级筹码的缺陷

半导体是所有技术变化的基础。PC时代是由强大的微处理器引入的。移动时代通过在智能手机中放置高性能，低功能芯片的进步。云时代具有庞大数据中心的处理器和记忆和存储库。尽管这些市场保持庞大且增长，但我们现在进入了由物联网（IoT），大数据和5G助力的AI时代，这是由新型的计算体系结构和芯片设计形成的。半导体的进步从未对全球经济的增长至关重要。

The stakes are high if we cannot continue to advance the semiconductor technology roadmap with high-performance logic and memory devices in the enormous volumes required for this new era. Getting from R&D to high-volume manufacturing of new technology nodes is a complex process gated primarily by the ability to detect and correct defects. The methods used by the industry to perform defect inspection and review have remained relatively the same for decades. Is it time to rethink our approaches?

This is the first blog in a series examining challenges around defect detection and correction. Any obstacles to advancement in the semiconductor industry ripple forward into the much larger global electronics ecosystem. The faster those obstacles can be overcome, the faster the world moves forward. Time is a critical factor.

Time is Money

Given the extraordinary cost of being in the semiconductor industry, its business imperatives revolve around time: time to development, time to volume production, time to market, and time to revenue. And the most critical parameter is time to yield. Even a small acceleration in the time it takes to get from R&D of new processes to the early ramp phase and then to high-volume manufacturing equates to billions of dollars in value for chipmakers (see Figure 1).

当然，情况也相反。在新计算时代，收益率提高成本，金钱和市场份额的延迟，这为世界有史以来最有价值的企业提供了延迟。

Chip Complexity

Defect detection is the gating factor in yield improvement. The faster yield-killing defects can be found, the faster they can be corrected. However, defects are getting harder to find. For example, ever-smaller line widths turn tiny nuisance particles into yield-killers. When building sophisticated 3D transistors, and when executing complex multi-patterning steps, small variances can multiply to produce yield-killing defects. This further complicates matters because a defect can be revealed long after its root cause occurred: every subsequent process step following the introduction of the defect is time and money wasted.

As the complexity of chips is rising and defects are becoming increasingly difficult to find, the industry should be inspecting more. But in reality, the exact opposite is happening—inspection steps are being limited. Why is that?

经济挑战

FAB经济模式成为这个关头的主要挑战。对于进步的每一个纳米，晶圆处理步骤的数量都会迅速增长。检查更多的步骤等于更多的检查成本。此外，用于查找缺陷的光学扫描仪的越来越复杂也增加了成本。每个扫描仪的成本更高等于每晶片扫描的成本更多（见图2）。

结果，工程师的检查步骤要少于他们仅仅防止其流程控制预算飞涨。当然，我imiting the number of inspection steps results in less of the data needed to accelerate defect detection, traceback, root cause analysis and correction—and thereby accelerate time to yield. Yet, these inspection costs are very real and cannot be wished away. The number of inspection steps inserted into the process recipe is one of the few points of cost control available. Fabs budget a certain amount of inspection dollars, engineers gather as much data as they can afford, and everyone hopes for the best.

今天使用的检查范式在非常不同的时间内开发了。摩尔的法律不仅是按计划运行的，而且在前几代人的晶圆地图上仅仅是滋扰的缺陷，现在是产量杀手。现实情况是，当我们应该检查更多时，该行业的检查较少，因此收集的数据较少（与挑战的复杂性相关）。我们需要的是一本新的流程控制剧本，可以加速时间屈服，而不会破坏Fab经济模型。对于半导体行业来说，这是一种创新。

In my next blog, I’ll describe the breakthroughs needed to revolutionize defect detection and correction in the AI Era.